A research team led by Prof. HU Yizhe and Prof. LIN Fujiang from the University of Science and Technology of China (USTC) of the Chinese Academy of Sciences (CAS) designed a low-jitter millimeter-wave all-digital phase-locked loop (CSS-ADPLL) chip based on an innovative charge-steering sampling (CSS) technique, which has been selected to participate in the 2023 Symposium on VLSI Technology and Circuits (VLSI Symposium) in Kyoto, Japan, from June 11th to 16th.

The VLSI Symposium is one of the renowned international conferences in the realm of large-scale integrated circuit chip design and process technology. The selection of the CSS-ADPLL chip underscores its technological superiority, derived from the cutting-edge charge-steering sampling (CSS) technique, particularly in achieving ultra-low jitter performance for millimeter-wave applications. 

The low-jitter millimeter-wave frequency synthesizer chip, which serves as a vital component in enabling 5G/6G millimeter-wave communications, delivers precise carrier signals for millimeter-wave communication systems. 

In this study, the researchers combined charge-steering sampling with a successive approximation register-type analog-to-digital converter (SAR-ADC) using the charge rudder sampling technique. This approach enabled the construction of a digital phase discriminator with exceptional phase-identification gain, high linearity, and multi-bit digital outputs. 

The CSS-ADPLL chip comprises a charge rudder discriminator (CSS-PD), a SAR-ADC, a digital filter, and a digital filter, and boasts a compact structure. It incorporates an ADC, digital filter, and numerically controlled oscillator, all contributing to excellent phase noise performance, fast locking speed, and minimal power consumption.