A physical limit of Boltzmann tyranny renders the subthreshold swing (SS) of a Si-based transistor no less than 60 mV/dec at room temperature, which leads to the reluctant reduction of power consumption, especially when Complementary Metal-Oxide-Semiconductor (CMOS) technology into sub-5 nm nodes.

By integrating ferroelectric materials in the High-K Metal Gate (HKMG) process, differential negative capacitances (NC) can be realized to break through the traditional Boltzmann tyranny and obtaining a steeper SS. Consequently, a smaller supply voltage and power consumption can be employed for the operation of IC.

The exploration of novel ferroelectric materials in mainstream FinFETs is still in the inception phase. In a study published in IEEE Electron Device Letters, researchers from Institute of Microelectronics of the Chinese Academy of Sciences developed new processes for the growth of Hafnium Zirconium Oxide (HZO) and integration in FinFETs etc., and demonstrated high performance NC p-FinFETs of different gate lengths featuring with an ultra-thin 3-nm-thick ferroelectric HZO.

During the growth of ultra-thin HZO, researchers carefully modulated both the atomic-layer deposition (ALD) process and post-annealing process.

Thanks to the low interface defect density and appropriate engineering of capacitance matching, as-fabricated FinFETs show greatly improved SS values, i.e., 34.5 mV/dec with 500 nm gate length (L_G) and 53 mV/dec with 20 nm L_G, and small hysteresis voltages, i.e., ~9 mV with 500 nm L_G and ~40 mV with 20 nm L_G.

The SS is much smaller than Boltzmann tyranny of 60 mV/dec and the hysteresis voltage is well controlled to an acceptable level. The ratio between I_on and I_off is as high as 1.23×10⁶.

NC FinFETs in this study pave the way for developing core transistors with almost identical performance while remarkably lowered power consumption in the future.